1. Field of the Invention
This invention relates to an electrostatic discharge (ESD) protection structure, and more particularly to a spike ESD structure for spike discharge without a dielectric layer in the discharging region.
2. Description of Related Art
In the fabrication of an integrated circuit (IC), ESD is one of the main factors causing IC damage. ESD is often seen in the work place. For example, when one walks on a carpet with semiconductor wafers, if relative humidity (RH) is high, an electrostatic voltage of about a few hundred volts may exist on one's body and wafers. If the RH is very low, the electrostatic voltage may be even as high as about a few thousand volts. If a conductive object occasionally contacts the wafers, a strong ESD could occur and damage the ICs on the wafers. ESD is an especially serious problem for fabrication of a complementary metal-oxide semiconductor (CMOS) device.
In order to protect wafers from ESD damage, many methods to solve the ESD problem have been proposed. The most common conventional method is to make an ESD protection circuit between input/output (I/O) pads and internal circuits so that the ESD does not damage the ICs fabricated on the wafers. Recently, the spike discharge ESD protection structure was investigated.
In above descriptions, the spike ESD phenomenon happens around the spike tips on a conductive object because the electric field on the spike tips is much stronger even though the electrostatic voltage is the same for the whole conductive object. The stronger electric field is due to a higher density of electrostatic surface charges on the spike tips, where the accumulated electrostatic surface charges are more easily triggered for discharging.
For example, FIG. 1 is a diagram schematically illustrating a conventional spike ESD structure. In FIG. 1, a structure IC devices basically includes a higher voltage source bus V.sub.DD 2, a lower voltage source bus V.sub.SS 6, and an input/output (I/O) pad 4. A pair of ESD spikes 8 and 10 is formed, and another pair of ESD spikes 12 and 14 is formed separately. Each of the ESD spike pairs provides a structure for discharging so that the IC is not affected and can not be damaged by ESD phenomena. This ESD structure thereby serves as a protection structure against ESD. Another example of a conventional protection method is to replace the ESD spikes 8, 10, 12, and 14 with a metal needle. FIG. 2 is a diagram schematically illustrating another conventional spike ESD structure. In FIG. 2, the box 15 and the box 16 are a pair of structures located between the voltage source buses 2, 6, and the I/O pad 4 in FIG. 1, such as a pair consisting of a V.sub.DD and an I/O PAD, a pair consisting of a V.sub.DD and a V.sub.SS, or a pair consisting of an I/O pad and a V.sub.SS. A spike ESD structure includes a metal needle 18, which can also behave as a spike ESD phenomenon. An even more effective protection against ESD includes several metal needles 18.
FIG. 3 is a cross-sectional view schematically illustrating a conventional spike ESD structure. In FIG. 3, a dielectric layer 22, with a number of metal layers 24 formed inside of it, is formed over a semiconductor substrate 20 to provide the spike ESD structure. Each of the metal layers 24 has its paired parts, separated from each other by a distance d. For example, two metal layers M.sub.N are paired and are separated by a distance "d" inside the dielectric layer 22. The gap between the metal pair M.sub.N is the place where the ESD occurs. Because the metal layers 24 are held by the dielectric layer 22, the distance "d" should be small enough to allow the ESD to occur through the dielectric layer 22.